This invention generally relates to apparatus and methods for synchronizing a first television signal to a second television signal. More particularly, the invention relates to apparatus and methods for generating a horizontal reset clock signal which is synchronized to a subcarrier locked clock. The invention is particularly useful for picture-in-picture video applications, although the scope of the invention is not limited thereto.
The increasing use of digital technology in television signal processing has resulted in particular requirements for the clock signals used by the digital circuitry. In particular, where stored images are to be inserted onto a screen (such as in picture-in-picture arrangements), a line-locked clock for controlling the insertion is desirable so that the inserted images will appear stationary. When using color information encoders and decoders, a subcarrier-locked clock is desirable so that the required digital circuitry can be simplified. In systems utilizing color information encoders and decoders as well as stored images, it is desirable to have a clock which is both line-locked and subcarrier locked, and in such situations, the PIP picture position in the generated image will be perfectly stationary.
In a standard RS170A television signal, the horizontal scanning frequency has a fixed predetermined relationship with respect to the subcarrier signal: F.sub.h =(2/455)F.sub.sc ; where F.sub.h is the horizontal frequency and F.sub.sc is the subcarrier frequency. In non-RS170A television signals, (e.g. from VCR's or test signal patterns), the F.sub.h and F.sub.sc signals are not derived from the same source, and hence have unrelated frequencies, such that the frequency F.sub.h may be significantly greater than or less than (2/455)F.sub.sc.
Where color information encoders and decoders are used, and in accord with the RS170A standard, signals at a multiple of the subcarrier such as 4F.sub.sc =14.3 MHz (910 times the horizontal frequency) which are locked to the subcarrier frequency are used. Since in the RS170A standard the horizontal scanning frequency has a fixed frequency relationship with respect to the subcarrier signal, and because a multiple of the subcarrier signal is locked to the subcarrier signal, in theory it should be possible to synchronize the asynchronous horizontal reset clock to the subcarrier multiple. In reality, such a synchronization is not straight-forward as the horizontal signal frequency may not be exactly 910 F.sub.sc, but may vary by +/-1 clock period of 4FSC, or more, due to noise induced phase jitter.
The standard circuitry for generating a synchronous horizontal reset signal from an asynchronous horizontal line signal is seen in FIG. 1. The provided circuit includes two D flip-flops 13 and 17, and a NAND gate 19. The D input to flip-flop 13 is the asynchronous horizontal signal, while a four times subcarrier frequency (FSC4) clock (FIG. 2a) is used as the clock input to both flip-flops 13 and 17. The Q output of flip-flop 13 is coupled to the D input of flip-flop 17, as well as to one input into NAND gate 19. The not Q output of flip-flop 17 is used as a second input into NAND gate 19. As seen in the timing diagrams of FIGS. 2b-2d in an initial state, the D input (FIG. 2b) and Q output (FIG. 2c) of flip-flop 13 are low, thereby providing a zero input to NAND gate 19 which provides an inactive high output (FIG. 2d). When the asynchronous signal goes high, at the next 4FSC clock, the high D input at flip-flop 13 is clocked over to the Q output of flip-flop 13. As a result, both inputs to NAND gate 19 are high, and NAND gate 19 provides a low output pulse. At the next FSC4 clock signal, the high D input at flip-flop 17 is clocked over to the Q output. Hence, the not Q output of flip-flop 17 goes low, and the NAND gate output returns to its high state. The cycle repeats only when the asynchronous signal goes high.
Difficulties with the standard circuitry arise where a pulse of the FSC4 clock occurs just after the rising edge of the asynchronous signal. In such circumstances denoted as the "indeterminate case" in FIGS. 2e-2g and as indicated by the dotted lines, it is possible that the change at the D input of flip-flop 13 will not have yet registered, and hence, the new status cannot be clocked across to the Q output until the next FSC4 clock signal. Such a situation could cause the output synchronous horizontal reset pulse to jitter (as indicated in FIG. 2g) relative to the main signal, resulting in a jittery picture-in-picture. While such a situation cannot be avoided where the horizontal clock is not related to the subcarrier clock (i.e. in situations where they were not originally derived from the same source), it is possible to avoid such jitter in standard RS-170A video applications where the frequencies of the horizontal line signal and the subcarrier are related. One manner of avoiding such jitter is to use complicated and expensive circuitry such as digital phase locked loops. The invention detailed below, however, provides an inexpensive manner of solving the jitter problem.